Add cache flush logic
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committed by
[Quy Anh] «Elliot» Nguyen
parent
18b2180322
commit
32c2b9440e
@@ -13,18 +13,64 @@
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#define BENCHMARK 0
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#endif
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#ifndef ROOFLINE
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#define ROOFLINE 0
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#endif
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#ifdef __x86_64__
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#include "./headers/tsc_x86.h"
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#include <immintrin.h>
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#define TRASH_BUFFER_SIZE (16ULL * 1024 * 1024 * 2) // Size of L3 cache : 16MB
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#define PAGE_SIZE 4096
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#endif
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#ifdef __aarch64__
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#include "./headers/kperf.h"
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#include <arm_acle.h>
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#define TRASH_BUFFER_SIZE (1502838784ULL * 2) // Size of SLC on M3 pro chips : 1.5GB
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#define PAGE_SIZE 16384
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#endif
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#define N_OBSTACLES 2
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#define WARMUP_ITERS 5
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#define NUM_REPS 11
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// Flushes caches by streaming reads through a large persistent buffer.
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long long flush_cache() {
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static volatile char *trash_buffer = nullptr;
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static bool initialized = false;
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if (!initialized) {
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trash_buffer = new volatile char[TRASH_BUFFER_SIZE];
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// Touch one byte per page once so pages are physically mapped. And we avoid paying the cost of page faults during cache trashing below.
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for (size_t i = 0; i < TRASH_BUFFER_SIZE; i += PAGE_SIZE) {
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trash_buffer[i] = 1;
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}
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initialized = true;
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}
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long long acc = 0;
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for (size_t i = 0; i < TRASH_BUFFER_SIZE; i += CACHE_BLOCK_SIZE) {
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// Access one byte per cache block is enough
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acc += trash_buffer[i];
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}
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#ifdef __x86_64__
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_mm_lfence();
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#endif
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#ifdef __aarch64__
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__isb(0xF);
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#endif
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asm volatile("" ::: "memory");
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return acc;
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}
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int main(int argc, const char *argv[]) {
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// Check that the correct number of arguments has been passed.
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//
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@@ -60,6 +106,10 @@ int main(int argc, const char *argv[]) {
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#if BENCHMARK
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#if ROOFLINE
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volatile long long trash_value;
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#endif
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#ifdef __aarch64__
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// Initialize ARM performance counters.
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kperf_init();
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@@ -86,6 +136,9 @@ int main(int argc, const char *argv[]) {
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for (int i = 0; i < NUM_REPS; i++) {
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Pedestrian *P = init_pedestrians(n_p);
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Board board = init_board_without_obstacles();
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#if ROOFLINE
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trash_value = flush_cache();
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#endif
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#ifdef __x86_64__
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myInt64 start = start_tsc();
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